CY2DL1504 Datasheet | Cypress

1:4 Differential LVDS Fanout Buffer with Selectable Clock Input na1:4 Differential LVDS Fanout Buffer with Selectable Clock Input Features - Select one of two differential (LVPECL, LVDS, HCSL, or CML) input pairs to distribute to four LVDS output pairs - Translates any single-ended input signal to 3.3 V LVDS levels with resistor bias on INx# input - 30 ps maximum output-to-output skew - 480 ps maximum propagation delay - 0.11 ps maximum additive RMS phase jitter at 156.25 MHz (12 k Hz to 20 MHz offset) - Up to 1.5 GHz operation - Output enable and synchronous clock enable functions - 20-pin TSSOP - 2.5 V or 3.3 V operating voltage [1] - mercial and industrial operating temperature range Functional Description The CY2DL1504 is an ultra-low noise, low-skew, low-propagation delay 1:4 differential LVDS fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DL1504 can select between two separate differential...