Description
The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion.
Features
- No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles.
- Supports up to 133-MHz bus operations with zero wait states.
- Data is transferred on every clock.
- Pin-compatible and functionally equivalent to ZBT™ devices.
- Internally self-timed output buffer control to eliminate the need
to use OE.
- Registered inputs for flow through operation.
- Byte Write capability.
- 3.3 V/2.5 V I/O power supply (VDDQ).
- Fast clock-to-output ti.
CY7C1371S-Cypress.pdf
