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PXA272 Datasheet

Interfacing Dual Port to Intel Embedded Processor

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Interfacing Cypress MoBL® Dual-Port to Intel® PXA272
Embedded Processor
Introduction
Table 1. PXA272 & CYDM256A16 Signal Equivalents
The PXA272 Embedded Processor of the Intel® PCA
(continued)
processor family is an integrated system-on-a-chip micropro-
cessor for high performance, dynamic and low-power
portable handheld and handset devices.
The Intel PXA272 processor includes a memory interface that
gives designers more flexibility as it supports a variety of
external memory types.
CYDM256A16 is an asynchronous MoBL® Dual-Port memory
PXA272 Signal CYDM256A16
(I/O)
Signal (I/O)
External I ODR[4:0] O
Devices
External O IRR[1:0] I
Devices
Function
Output Drive Register
Input Read Register
from Cypress Semiconductor. It has a 256-Kbit shared
M/S I
Master/Slave
memory array with two 16-bit data buses. The shared
Select: pulled up to VCC
memory structure allows independent access from both ports
to 32K address locations. The device is available in -35 and
Layout Guidelines
-55 speed grades in both commercial and industrial temper-
ature ranges. Internal arbitration logic is also available to
Figure 1 below shows the physical wiring between the
decide which port gets access when both ports try to access
PXA272 processor and the MoBL Dual-Port CYDM256A16.
the same memory location at the same time.
Either port of the MoBL Dual-Port may be used. Table 2
shows the list of unused PXA272 EMI pins.
The MoBL Dual-Port can act as an interconnect between two
processing elements that share data while operating at
www.DataSheet4U.comdifferent speeds. This application note describes how to
DQ[15:0]
MD[15:0]
interface the CYDM256A16 to the Intel PXA272.
A[14:0]
MA[14:0]
CE CSx
External Memory Interface (EMI)
The Intel PXA272’s External Memory Interface is a 16/32-bit
OE OE
R/W WE
UB DQM[1]
interface and it can be configured to gluelessly interface to
LB DQM[0]
Cypress low-power MoBL Dual-Ports.
INT GPIO
The Cypress MoBL Dual-Port CYDM256A16 has a standard
asynchronous SRAM interface. Table 1 lists the signal
connections between Intel PXA272 and Cypress MoBL
Dual-Port CYDM256A16.
Table 1. PXA272 & CYDM256A16 Signal Equivalents
BUSY
SFEN
M/S
IRR
ODR
Cypress MoBL Dual-Port
CYDM256A16
RDY
Vcc GPIO
Ext. Inputs
Ext. Outputs
Intel Embedded Processor
PXA272
PXA272 Signal CYDM256A16
(I/O)
Signal (I/O)
Function
Figure 1. Wiring Diagram of PXA272 to CYDM256A16
CSx
WE
OE
MA[14:0]
O
O
O
O
CE
R/W
OE
A[14:0]
I
I
I
I
Chip select
Write enable
Output enable
Address
Table 2. Unused Intel PXA272 Signals
MA[25:15]
CLK
NC
NC
MD[15:0] I/O DQ[15:0] I/O
DQM[1] O UB I
DQM[0] O LB I
RDY
I BUSY I/O
GPIOx I
INT O
Data
Upper byte enable
Lower byte enable
Busy Signal
Mailbox Interrupt
Voltage Compatibility
Cypress MoBL Dual-Ports have operating voltages of 1.8V,
2.5V, and 3.0V, while the Intel PXA272 supports 1.8V, 2.5V
and 3.3V I/O supply voltages. Thus, the Cypress MoBL
Dual-Ports are compatible with the Intel processor PXA272
when both devices operate at the same voltage.
GPIOx O SFEN I Special Function enable
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Revised March 31, 2005
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Cypress Semiconductor Electronic Components Datasheet

PXA272 Datasheet

Interfacing Dual Port to Intel Embedded Processor

No Preview Available !

www.DataSheet4U.com
Interfacing Cypress MoBL™ Dual-Port to
Intel PXA272 Embedded Processor
PXA272 Register Settings
Read Operation
In order to properly interface the PXA272 to the Cypress
MoBL Dual-Port, the MSCx register of the processor needs
to be configured, while the rest of the registers can be left in
their default settings. Table 3 shows the recommended MSCx
register setting, assuming the PXA272 processor is running
at 520 MHz and connected to the CYDM256A16-55. The
same analysis can be used to interface the processor to
Dual-Ports with the -35 speed grade.
Table 3. MSCx Register Settings
Field
RTx
RBW
RDF
RDN
RRR
RBUFF
Value
Description
001b Type of memory: SRAM
1b Data bus width: 16 bits
1111b ROM/SRAM delay first access: 30*
Clock pulse equivalent of processor
1111b ROM/SRAM delay next access: 30*
clock pulse equivalent of processor
101b ROM/SRAM Recovery Time
0b Fast/Slow device: Slow Device
With an internal reference clock of 520 MHz (1.923-ns clock
period), the register settings required to set up proper read
operations are shown in Table 3. RDF (ROM Delay First
access), which defines the number of wait states inserted in
a read cycle, needs to be 30 times the REF_CLK clock cycle.
This essentially extends the chip select enable duration of a
read cycle to 30 x REF_CLK = 57.7ns. Figure 2 shows the
timing details of a read operation between the PXA272 and
MoBL Dual-Port.
To initiate a read operation, the shortest read cycle needs to
be at least tRC. The processor will also need to wait for the
maximum of tAA, tABE and tACE for the data to propagate back
from the MoBL Dual-Port. The CYDM256A16-55 MoBL
Dual-Port has a tRC= 55 ns, tAA = 45ns and tABE = 45 ns.
Read access time for the SRAM controller is configured
through the RDF field of MSCx register. Referring to the Intel
documentation:
(RDFx+2)*(Time period of processor clock) > Read Cycle
time of the MoBL Dual-Port.
=> RDFx > ((Read Cycle Time of MoBL Dual-Port/Time
period of processor clock) – 2.
=> RDFx > (55ns/1.923) – 2 = 28.6 – 2 = 26.6.
Timing Considerations
=> RDFx > 26.6
This section of the application note provides a sample timing
analysis of read and write operations with the PXA272
Considering the worst case, the decoded value of RDF
should be set to 30 for extra timing margin (RDF=”1111”).
processor and MoBL Dual-Port CYDM256A16-55. Assume
that the system clock of the processor runs at the maximum
www.DataSheet4U.comfrequency of 520 MHz. Please note that the register setting
Subsequent read operation:
Before starting a subsequent MoBL Dual-Port read, the
may vary depending on the speed of the desired memory as
processor should wait for at least tHZCE = 20ns (max). To
well as the system clock frequency (refer to PXA27x
achieve this, we need to set the RRRx (ROM/SRAM recovery
Processor Family Developers Manual for detail).
time) field of MSCx register. Referring to the Intel documen-
tation:
tOFF > (RRRx*2+1)*Processor Clock Period.
Processor
Signal
CSx
MoBL Dual-Port
Signals
CE
tCLK
tRC[1]
RDFx X tCLK[2]
MD[14:0]
OE
MD[15:0]
DQM[1:0]
A[14:0]
OE
DQ[15:0]
UB/LB
RDFx X tCLK[2]
tAA[1]
RRRx X tCLK[2]
tSD[1]
tHZCE[1]
F6[2] F7[2]
R/W
WE
Notes:
1. Required by the MoBL Dual-Port for proper read.
2. Provided by the Processor.
Figure 2. Read Cycle
2
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Part Number PXA272
Description Interfacing Dual Port to Intel Embedded Processor
Maker Cypress
Total Page 4 Pages
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