Interfacing Cypress MoBL™ Dual-Port to
Intel PXA272 Embedded Processor
PXA272 Register Settings
In order to properly interface the PXA272 to the Cypress
MoBL Dual-Port, the MSCx register of the processor needs
to be configured, while the rest of the registers can be left in
their default settings. Table 3 shows the recommended MSCx
register setting, assuming the PXA272 processor is running
at 520 MHz and connected to the CYDM256A16-55. The
same analysis can be used to interface the processor to
Dual-Ports with the -35 speed grade.
Table 3. MSCx Register Settings
001b Type of memory: SRAM
1b Data bus width: 16 bits
1111b ROM/SRAM delay first access: 30*
Clock pulse equivalent of processor
1111b ROM/SRAM delay next access: 30*
clock pulse equivalent of processor
101b ROM/SRAM Recovery Time
0b Fast/Slow device: Slow Device
With an internal reference clock of 520 MHz (1.923-ns clock
period), the register settings required to set up proper read
operations are shown in Table 3. RDF (ROM Delay First
access), which defines the number of wait states inserted in
a read cycle, needs to be 30 times the REF_CLK clock cycle.
This essentially extends the chip select enable duration of a
read cycle to 30 x REF_CLK = 57.7ns. Figure 2 shows the
timing details of a read operation between the PXA272 and
To initiate a read operation, the shortest read cycle needs to
be at least tRC. The processor will also need to wait for the
maximum of tAA, tABE and tACE for the data to propagate back
from the MoBL Dual-Port. The CYDM256A16-55 MoBL
Dual-Port has a tRC= 55 ns, tAA = 45ns and tABE = 45 ns.
Read access time for the SRAM controller is configured
through the RDF field of MSCx register. Referring to the Intel
(RDFx+2)*(Time period of processor clock) > Read Cycle
time of the MoBL Dual-Port.
=> RDFx > ((Read Cycle Time of MoBL Dual-Port/Time
period of processor clock) – 2.
=> RDFx > (55ns/1.923) – 2 = 28.6 – 2 = 26.6.
=> RDFx > 26.6
This section of the application note provides a sample timing
analysis of read and write operations with the PXA272
Considering the worst case, the decoded value of RDF
should be set to 30 for extra timing margin (RDF=”1111”).
processor and MoBL Dual-Port CYDM256A16-55. Assume
that the system clock of the processor runs at the maximum
www.DataSheet4U.comfrequency of 520 MHz. Please note that the register setting
Subsequent read operation:
Before starting a subsequent MoBL Dual-Port read, the
may vary depending on the speed of the desired memory as
processor should wait for at least tHZCE = 20ns (max). To
well as the system clock frequency (refer to PXA27x
achieve this, we need to set the RRRx (ROM/SRAM recovery
Processor Family Developers Manual for detail).
time) field of MSCx register. Referring to the Intel documen-
tOFF > (RRRx*2+1)*Processor Clock Period.
RDFx X tCLK
RDFx X tCLK
RRRx X tCLK
1. Required by the MoBL Dual-Port for proper read.
2. Provided by the Processor.
Figure 2. Read Cycle