CY2302 Datasheet (Frequency Multiplier and Zero Delay Buffer)

Part: CY2302
Manufacturer: Cypress (official site)
Size: 323.60 KB

CY2302 Key Features

90 ps typical jitter OUT2
200 ps typical jitter OUT1
65 ps typical output-to-output skew
90 ps typical propagation delay
Voltage range: 3.3 V±5%, or 5 V±10%
Output frequency range: 5 MHz to 133 MHz
Two outputs
Configuration options allow various multiplications of the
Available in 8-pin SOIC package
198 Champion Court Document #: 38-07154 Rev. -E

Related Cypress Datasheets

Part Number	Description
CY2300	Phase-Aligned Clock Multiplier
CY2303	Phase-Aligned Clock Multiplier
CY2305C	Zero Delay Buffers
CY2309C	Zero Delay Buffers
CY2313ANZ	3.3V SDRAM Buffer for Desktop PCs with 3 DIMMs

CY2302 Description

The output signals are synchronized to this signal. This input must be fed by one of the outputs (OUT1 or OUT2) to ensure proper functionality. If the trace between FBIN and the output pin being used for feedback is equal in length to the traces between the outputs and the signal destinations, then the signals received at the destinations are synchronized to the REF signal input (IN).