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CY28351 Datasheet Differential Clock Buffer/Driver

Manufacturer: Cypress (now Infineon)

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General Description

This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels.

This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT).

The clock outputs are individually controlled by the serial inputs SCLK and SDATA.

Overview

CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant.

Key Features

  • Supports 333-MHz and 400-MHz DDR SDRAM.
  • 60-.
  • 200-MHz operating frequency.
  • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM.

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