CY28359 Datasheet | Cypress

Features - Dual 1- to 3-output buffer/driver - Supports up to 2 DDR DIMMs - Outputs are individually enabled/disabled - Low-skew outputs (< 100 ps) - Supports 266-MHz, 333-MHz and 400-MHz DDR SDRAM - SMBus Read and Write support - Space-saving 28-pin SSOP package Functional Description The CY28359 is a 2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 6 differential outputs. Designers can configure these outputs to support up to two DDR DIMMs. The CY28359 can be used in conjunction with the CY28326 or similar clock synthesizer for the VIA P4X600 chipset. The CY28359 also includes an SMBus interface which can enable or disable each output clock. On power-up, all output clocks are enabled. Block Diagram BUF_INA FB_OUTA DDRAT0 DDRAC0 DDRAT1 DDRAC1 DDRAT2 DDRAC2 DDRBT0 DDRBC0 DDRBT1 DDRBC1 DDRBT2 DDRBC2 FB_OUTB Pin Configuration FB_OUTB BUF_INB DDRBT0 DDRBC0 DDRBT1 DDRBC1 VDD VSS FB_OUTA BUF_INA VSS DDRAT0 DDRAC0 DDRAT1 SDATA SEL_ADDR SCLK SMBus Decoding BUFF_INB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS SEL_ADDR DDRBT2 DDRBC2 VSS VDD DDRAT2 DDRAC2 SDATA SCLK VSS VDD DDRAC1 28 PIN SSOP Cypress Semiconductor Corporation Document #: 38-07636 Rev. - - - 3901 North First Street - San Jose, CA 95134 - 408-943-2600 Revised February 16, 2004 PRELIMINARY Pin Description Pin 10 2 13,15,20 4,6,24 12,14,21 3,5,25 9 1 18 19 26 7,16,22,28 8,11,17,23,27 Name BUF_INA, BUF_INB DDRA[0:2]C DDRB[0:2]C DDRA[0:2]T DDRB[0:2]T FB_OUTA FB_OUTB SCLK SDATA SEL_ADDR VDD2.5 VSS PWR VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 VDD2.5 I/O I O O O I I/O I Description Reference input from chipset. 2.5V input. Clock outputs. These outputs provide plementary copies of BUF_INA & BUF_INB, respectively. Clock outputs. These outputs provide copies of BUF_INA & BUF_INB, respectively. Feedback clock for chipset SMBus clock input. Has pull-up resistor SMBus data input. Has pull-up resistor Address Select Pin....