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CY28351 - Differential Clock Buffer/Driver

General Description

This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels.

This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT).

Key Features

  • Supports 333-MHz and 400-MHz DDR SDRAM.
  • 60-.
  • 200-MHz operating frequency.
  • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM.

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Part Number Description
CY28352 Differential Clock Buffer/Driver
CY28354-400 210-MHz 24-Output Buffer
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the outputs to the clock input • Conforms to the DDRI specification • Spread Aware for electromagnetic interference (EMI) reduction • 48-pin SSOP package Description This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels.