CY28351 Description
This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels. This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT). The clock outputs are individually controlled by the serial inputs SCLK and SDATA.
CY28351 Key Features
- Supports 333-MHz and 400-MHz DDR SDRAM
- 200-MHz operating frequency
- Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM
CY28351 Applications
- Distributes one clock input to ten differential outputs
- External feedback pin (FBIN) is used to synchronize the outputs to the clock input
- Conforms to the DDRI specification
- Spread Aware for electromagnetic interference (EMI) reduction