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CY28358 Datasheet 200-MHz Differential Clock Buffer/Driver

Manufacturer: Cypress (now Infineon)

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General Description

This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential output levels.

This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT.

The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN.

Overview

58 PRELIMINARY CY28358 200-MHz Differential Clock Buffer/Driver.

Key Features

  • Up to 200 MHz operation.
  • Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM.

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