CY62157H Datasheet | Cypress

CY62157H Mo BL® 8-Mbit (512K words × 16-bit) Static RAM with Error-Correcting Code (ECC) 8-Mbit (512K words × 16-bit) Static RAM with Error-Correcting Code (ECC) Features - Ultra-low standby current - Typical standby current: 5.5A - Maximum standby current: 16 A - High speed: 45 ns - Voltage range: 2.2 V to 3.6 V - Embedded Error-Correcting Code (ECC) for single-bit error correction - 1.0 V data retention - Transistor-transistor logic (TTL) patible inputs and outputs - Available in Pb-free 48-ball VFBGA and 48-pin TSOP I packages Functional Description CY62157H is a high-performance CMOS low-power (Mo BL) SRAM device with Embedded Error-Correcting Code. ECC logic can detect and correct single bit error in accessed location. This device is offered in dual chip enable option. Dual chip enable devices are accessed by asserting both chip enable inputs - CE1 as LOW and CE2 as HIGH. Data writes are performed by asserting the Write Enable input (WE LOW), and providing the data and address on device data (I/O0 through I/O15) and address (A0 through A18) pins respectively. The Byte High/Low Enable (BHE, BLE) inputs control byte writes, and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Read data is accessible on I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE, BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1 HIGH / CE2 LOW for dual chip enable device), or control signals are de-asserted (OE, BLE, BHE). These devices also have a unique “Byte Power down” feature, where, if both the Byte Enables (BHE and BLE) are disabled, the devices...