CY7C1215F Datasheet 1-Mb (32K x 32) Pipelined Sync SRAM

Manufacturer: Cypress (now Infineon)

Datasheet Details

s and Truth Table for further details).

Write cycles can be one to four bytes wide as controlled by the Byte Write control inputs.

GW when active LOW causes all bytes to be written.

CY7C1215F www.DataSheet4U.com 1-Mb (32K x 32) Pipelined Sync.

Registered inputs and outputs for pipelined operation.
32K × 32 common I/O architecture.
3.3V core power supply.
3.3V I/O operation.
Fast clock-to-output times.
3.5ns (for 166-MHz device).
4.0 ns (for 133-MHz device).
Provide high-performance 3-1-1-1 access rate.
User-selectable burst counter supporting Intel Pentium® interleaved or linear burst sequences.
Separate processor and controller address strobes.

Part Number	Description
CY7C1215H	1-Mbit (32K x 32) Pipelined Sync SRAM
CY7C1212F	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H	1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F	1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H	1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1217F	1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1217H	1-Mbit (32K x 36) Flow-Through Sync SRAM
CY7C1218F	1-Mb (32K x36) Pipelined Sync SRAM
CY7C1218H	1-Mbit (32K x36) Pipelined Sync SRAM
CY7C1219F	1-Mbit (32K x 36) Pipelined DCD Sync SRAM