CY7C1219H Datasheet - Cypress Semiconductor

1-Mbit (32K x 36) Pipelined DCD Sync SRAM

CY7C1219H Features

* Registered inputs and outputs for pipelined operation

* Optimal for performance (Double-Cycle deselect)

* Depth expansion without wait state

* 32K × 36-bit common I/O architecture

* 3.3V core power supply (VDD)

* 2.5V/3.3V I/O power supply (VDDQ)

CY7C1219H General Description

1] The CY7C1219H SRAM integrates 32K x 36 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresse.

CY7C1219H Datasheet (398.39 KB)

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CY7C1219H

Manufacturer:

Cypress Semiconductor

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398.39 KB

Description:

1-mbit (32k x 36) pipelined dcd sync sram.

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CY7C1219H 1-Mbit 32K Pipelined DCD Sync SRAM Cypress Semiconductor

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CY7C1219H Features

CY7C1219H General Description

Datasheet Details

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