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CY7C1265XV18 - 36-Mbit QDR II+ Xtreme SRAM Four-Word Burst Architecture

Download the CY7C1265XV18 datasheet PDF (CY7C1263XV18 included). The manufacturer datasheet provides complete specifications, pinout details, electrical characteristics, and typical applications for 36-mbit qdr ii+ xtreme sram four-word burst architecture.

Features

  • Separate Independent Read and Write Data Ports.
  • Supports concurrent transactions.
  • 633 MHz Clock for High Bandwidth.
  • Four-word Burst for Reducing Address Bus Frequency.
  • Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz.
  • Available in 2.5 Clock Cycle Latency.
  • Two Input Clocks (K and K) for precise DDR Timing.
  • SRAM uses rising edges only.
  • Echo Clocks (CQ and CQ) simplify Data Capture in High Speed Sy.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7C1263XV18-CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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CY7C1263XV18 CY7C1265XV18 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) 36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features ■ Separate Independent Read and Write Data Ports ❐ Supports concurrent transactions ■ 633 MHz Clock for High Bandwidth ■ Four-word Burst for Reducing Address Bus Frequency ■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 1266 MHz) at 633 MHz ■ Available in 2.
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