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CY7C1294DV18 Datasheet (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: www.DataSheet4U.com CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst.

Download the CY7C1294DV18 datasheet PDF. This datasheet also includes the CY7C1292DV18 variant, as both parts are published together in a single manufacturer document.

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General Description

The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.

Key Features

  • Separate Independent Read and Write data ports.
  • Supports concurrent transactions.
  • 250-MHz clock for high bandwidth.
  • 2-Word Burst on all accesses.
  • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz.
  • Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges only.
  • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1292DV18 (CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
CY7C1297F 1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1298F 1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1298H 1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1212F 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1212H 1-Mbit (64K x 18) Pipelined Sync SRAM
CY7C1214F 1-Mb (32K x 32) Flow-Through Sync SRAM
CY7C1214H 1-Mbit (32K x 32) Flow-Through Sync SRAM
CY7C1215F 1-Mb (32K x 32) Pipelined Sync SRAM
CY7C1215H 1-Mbit (32K x 32) Pipelined Sync SRAM