CY7C1298F Datasheet (1-Mbit (64K x 18) Pipelined DCD Sync SRAM)

Part: CY7C1298F
Manufacturer: Cypress (official site)
Size: 361.00 KB

CY7C1298F Key Features

Registered inputs and outputs for pipelined operation
Optimal for performance (Double-Cycle deselect)
Depth expansion without wait state
64K × 18-bit mon I/O architecture
3.3V -5% and +10% core power supply (VDD)
3.3V I/O supply (VDDQ)
Fast clock-to-output times
3.5ns (for 166-MHz device)
4.0ns (for 133-MHz device)
Provide high-performance 3-1-1-1 access rate

Related Cypress Datasheets

Part Number	Description
CY7C1298H	1-Mbit (64K x 18) Pipelined DCD Sync SRAM
CY7C1292DV18	(CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
CY7C1294DV18	(CY7C1292DV18 / CY7C1294DV18) SRAM 2-Word Burst Architecture
CY7C1297F	1-Mbit (64K x 18) Flow-Through Sync SRAM
CY7C1212F	1-Mbit (64K x 18) Pipelined Sync SRAM

CY7C1298F Description

[1] The CY7C1298F SRAM integrates 65,536x18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control...