CY7C1302DV25 Datasheet 9-Mbit Burst of Two Pipelined SRAMs

Manufacturer: Cypress (now Infineon)

Datasheet Details

Part number	CY7C1302DV25
Manufacturer	Cypress (now Infineon)
File Size	245.82 KB
Description	9-Mbit Burst of Two Pipelined SRAMs
Download	CY7C1302DV25 Download (PDF)

The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture.

QDR architecture consists of two separate ports to access the memory array.

The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations.

www.DataSheet4U.com PREMILINARY CY7C1302DV25 9-Mbit Burst of Two Pipelined SRAMs with QDR™.

Separate independent Read and Write data ports.
Supports concurrent transactions.
167-MHz clock for high bandwidth.
2.5 ns clock-to-Valid access time.
2-word burst on all accesses.
Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two output clocks (C and C) account for clock skew an.

Part Number	Description
CY7C1302CV25	9-Mbit Burst of Two Pipelined SRAMs
CY7C130	1K x 8 Dual-Port Static RAM
CY7C1303BV18	18-Mbit Burst of 2 Pipelined SRAM
CY7C1303BV25	18-Mbit Burst of Two-Pipelined SRAM
CY7C1304DV25	9-Mbit Burst of 4 Pipelined SRAM
CY7C1305BV18	18-Mbit Burst of 4 Pipelined SRAM
CY7C1305BV25	18-Mbit Burst of 4 Pipelined SRAM
CY7C1306BV18	18-Mbit Burst of 2 Pipelined SRAM
CY7C1307BV18	18-Mbit Burst of 4 Pipelined SRAM
CY7C1307BV25	18-Mbit Burst of 4 Pipelined SRAM