CY7C1302DV25 - 9-Mbit Burst of Two Pipelined SRAMs

Product Overview

Cypress Semiconductor

Part number	CY7C1302DV25
Manufacturer	Cypress Semiconductor
File Size	245.82 KB
Description	9-Mbit Burst of Two Pipelined SRAMs
Datasheet	CY7C1302DV25 Datasheet
Additional preview pages of the CY7C1302DV25 datasheet.

The CY7C1302DV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture.

Separate independent Read and Write data ports.
Supports concurrent transactions.
167-MHz clock for high bandwidth.
2.5 ns clock-to-Valid access time.
2-word burst on all accesses.
Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two output clocks (C and C) account for clock skew an.

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Published: Dec 8, 2006 |