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CY7C1311CV18 Datasheet (CY7C1x1xCV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1311CV18, CY7C1911CV18 CY7C1313CV18, CY7C1315CV18 18-Mbit QDR™-II SRAM 4-Word Burst.

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General Description

The CY7C1311CV18, CY7C1911CV18, CY7C1313CV18, and CY7C1315CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Key Features

  • Configurations CY7C1311CV18.
  • 2M x 8 CY7C1911CV18.
  • 2M x 9 CY7C1313CV18.
  • 1M x 18 CY7C1315CV18.
  • 512K x 36 Separate independent read and write data ports.
  • Supports concurrent transactions 300 MHz clock for high bandwidth 4-word burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 600 MHz) at 300 MHz Two input clocks (K and K) for precise DDR timing.
  • SRAM uses rising edges onl.

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