CY7C1338 Key Features
- Supports 117-MHz microprocessor cache systems with zero wait states
- 128K by 32 mon I/O
- Fast clock-to-output times
- 7.5 ns (117-MHz version)
- Two-bit wraparound counter supporting either interleaved or linear burst sequence
- Separate processor and controller address strobes provide direct interface with the processor and external cache control
- Synchronous self-timed write
- Asynchronous output enable
- 3.3V I/Os
- JEDEC-standard pinout