CY7C1347B - 128K x 36 Synchronous-Pipelined Cache RAM

Cypress Semiconductor

Datasheet Details

Part number	CY7C1347B
Manufacturer	Cypress Semiconductor
File Size	910.50 KB
Description	128K x 36 Synchronous-Pipelined Cache RAM
Datasheet	CY7C1347B_CypressSemiconductor.pdf

The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic.

Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states.
Fully registered inputs and outputs for pipelined operation.
128K by 36 common I/O architecture.
3.3V core power supply.
2.5V/3.3V I/O operation.
Fast clock-to-output times.
3.5 ns (for 166-MHz device).
4.0 ns (for 133-MHz device).
5.5 ns (for 100-MHz device) User-se.

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Published: Oct 16, 2006 |