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CY7C1347B Datasheet - Cypress Semiconductor

128K x 36 Synchronous-Pipelined Cache RAM

CY7C1347B Features

* Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states

* Fully registered inputs and outputs for pipelined operation

* 128K by 36 common I/O architecture

* 3.3V core power supply

* 2.5V/3.3V I/O operation

* Fast clock-to-outp

CY7C1347B General Description

The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. Logic Block Diagram CLK ADV ADSC ADSP A[16:0] GW BWE BW 3 BW2 BW1 BW0 CE1 CE2 CE3 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D 15 .

CY7C1347B Datasheet (910.50 KB)

Preview of CY7C1347B PDF

Datasheet Details

Part number:

CY7C1347B

Manufacturer:

Cypress Semiconductor

File Size:

910.50 KB

Description:

128k x 36 synchronous-pipelined cache ram.

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CY7C1347B 128K Synchronous-Pipelined Cache RAM Cypress Semiconductor

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