CY7C1347D Datasheet | Cypress

.. 128K x 36 Synchronous-Pipelined Cache SRAM Features - Fast access times: 2.5 and 3.5 ns - Fast clock speed: 250, 225, 200, and 166 MHz - 1.5-ns set-up time and 0.5-ns hold time - Fast OE access times: 2.5 ns and 3.5 ns - Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) - 3.3V - 5% and +10% power supply - 3.3V or 2.5V I/O supply - 5V tolerant inputs except I/Os - Clamp diodes to VSS at all inputs and outputs - mon data inputs and data outputs - Byte Write Enable and Global Write control - Three chip enables for depth expansion and address pipeline - Address, data, and control registers - Internally self-timed Write Cycle - Burst control pins (interleaved or linear burst sequence) - Automatic power-down for portable applications - JTAG boundary scan - JEDEC standard pinout - Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst...