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CY7C1345G - 4-Mbit Flow-Through Sync SRAM

Datasheet Summary

Description

The CY7C1345G is a 128K × 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic.

The maximum access delay from clock rise is 8.0 ns (100 MHz version).

Features

  • 128K × 36 common I/O.
  • 3.3 V core power supply (VDD).
  • 2.5 V or 3.3 V I/O supply (VDDQ).
  • Fast clock-to-output times.
  • 8.0 ns (100 MHz version).
  • Provide high performance 2-1-1-1 access rate.
  • User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences.
  • Separate processor and controller address strobes.
  • Synchronous self timed write.
  • Asynchronous output enable.
  • Available in Pb-free 100-pin TQFP package.
  • ZZ sle.

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Datasheet preview – CY7C1345G

Datasheet Details

Part number CY7C1345G
Manufacturer Cypress Semiconductor
File Size 1.02 MB
Description 4-Mbit Flow-Through Sync SRAM
Datasheet download datasheet CY7C1345G Datasheet
Additional preview pages of the CY7C1345G datasheet.

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Full PDF Text Transcription

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CY7C1345G 4-Mbit (128K × 36) Flow-Through Sync SRAM 4-Mbit (128K × 36) Flow-Through Sync SRAM Features ■ 128K × 36 common I/O ■ 3.3 V core power supply (VDD) ■ 2.5 V or 3.3 V I/O supply (VDDQ) ■ Fast clock-to-output times ❐ 8.0 ns (100 MHz version) ■ Provide high performance 2-1-1-1 access rate ■ User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences ■ Separate processor and controller address strobes ■ Synchronous self timed write ■ Asynchronous output enable ■ Available in Pb-free 100-pin TQFP package ■ ZZ sleep mode option Functional Description The CY7C1345G is a 128K × 36 synchronous cache RAM designed to interface with high speed microprocessors with minimum glue logic. The maximum access delay from clock rise is 8.0 ns (100 MHz version).
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