CY7C1347G Datasheet | Cypress

.. PRELIMINARY 4-Mbit (128K x 36) Pipelined Sync SRAM Features - Fully registered inputs and outputs for pipelined operation - 128K by 36 mon I/O architecture - 3.3V core power supply - 2.5V/3.3V I/O operation - Fast clock-to-output times - 2.6 ns (for 250-MHz device) - 2.6 ns (for 225-MHz device) - 2.8 ns (for 200-MHz device) - 3.5 ns (for 166-MHz device) - 4.0 ns (for 133-MHz device) - 4.5 ns (for 100-MHz device) - User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences - Separate processor and controller address strobes - Synchronous self-timed writes - Asynchronous output enable - Lead-Free 100-pin TQFP, 119-pin BGA and 165-pin f BGA packages - “ZZ” Sleep Mode option and Stop Clock option - Available in Industrial and mercial temperature ranges Functional Description[1] The CY7C1347G is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250-MHz device). CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the Power PC®. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations...