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CY7C1347G Datasheet 4-Mbit (128K x 36) Pipelined Sync SRAM

Manufacturer: Cypress (now Infineon)

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General Description

[1] The CY7C1347G is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic.

CY7C1347G I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.

All synchronous inputs pass through input registers controlled by the rising edge of the clock.

Overview

www.DataSheet4U.com PRELIMINARY CY7C1347G 4-Mbit (128K x 36) Pipelined Sync.

Key Features

  • Fully registered inputs and outputs for pipelined operation.
  • 128K by 36 common I/O architecture.
  • 3.3V core power supply.
  • 2.5V/3.3V I/O operation.
  • Fast clock-to-output times.
  • 2.6 ns (for 250-MHz device).
  • 2.6 ns (for 225-MHz device).
  • 2.8 ns (for 200-MHz device).
  • 3.5 ns (for 166-MHz device).
  • 4.0 ns (for 133-MHz device).
  • 4.5 ns (for 100-MHz device).
  • User-selectable burst counter supporting In.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM
CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM
CY7C1347F 4-Mbit (128K x 36) Pipelined Sync SRAM
CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM
CY7C13451G 4-Mbit Flow-Through Sync SRAM
CY7C1345G 4-Mbit Flow-Through Sync SRAM
CY7C130 1K x 8 Dual-Port Static RAM
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