CY7C1347G - 4-Mbit (128K x 36) Pipelined Sync SRAM

Cypress Semiconductor

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Datasheet Details

Part number	CY7C1347G
Manufacturer	Cypress Semiconductor
File Size	527.03 KB
Description	4-Mbit (128K x 36) Pipelined Sync SRAM
Datasheet	CY7C1347G_CypressSemiconductor.pdf

CY7C1347G Product details

Description

1] The CY7C1347G is a 3.3V, 128K by 36 synchronous-pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic.CY7C1347G I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V.All synchronous inputs pass through input registers controlled by the rising edge of the clock.All data outputs pass through output registers controlled by the rising edge of the clock.Maximum access delay from the clock rise is 2.6 ns (

Features

Fully registered inputs and outputs for pipelined operation.
128K by 36 common I/O architecture.
3.3V core power supply.
2.5V/3.3V I/O operation.
Fast clock-to-output times.
2.6 ns (for 250-MHz device).
2.6 ns (for 225-MHz device).
2.8 ns (for 200-MHz device).
3.5 ns (for 166-MHz device).
4.0 ns (for 133-MHz device).
4.5 ns (for 100-MHz device).
User-selectable burst counter supporting In.

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Other Datasheets by Cypress Semiconductor

CY7C1347B - 128K x 36 Synchronous-Pipelined Cache RAM
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Published: Oct 16, 2006 |