CY7C1347B Datasheet | Cypress

.. 1CY7C1347 128K x 36 Synchronous-Pipelined Cache RAM Features - Supports 100-MHz bus for Pentium and Power PC™ operations with zero wait states - Fully registered inputs and outputs for pipelined operation - 128K by 36 mon I/O architecture - 3.3V core power supply - 2.5V/3.3V I/O operation - Fast clock-to-output times - 3.5 ns (for 166-MHz device) - 4.0 ns (for 133-MHz device) - - - - - - - - 5.5 ns (for 100-MHz device) User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100 TQFP pinout “ZZ” Sleep Mode option and Stop Clock option Available in Industrial and mercial Temperature ranges The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device). The CY7C1347B supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the Power PC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous...