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CY7C1347B - 128K x 36 Synchronous-Pipelined Cache RAM

General Description

The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic.

Key Features

  • Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states.
  • Fully registered inputs and outputs for pipelined operation.
  • 128K by 36 common I/O architecture.
  • 3.3V core power supply.
  • 2.5V/3.3V I/O operation.
  • Fast clock-to-output times.
  • 3.5 ns (for 166-MHz device).
  • 4.0 ns (for 133-MHz device).
  • 5.5 ns (for 100-MHz device) User-se.

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CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com 1CY7C1347 CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features • Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • • • • • • • — 5.