Datasheet Summary
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PRELIMINARY
CY7C1355C CY7C1357C
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture
Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
- Can support up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- Byte Write capability
- 3.3V/2.5V I/O power supply
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
- 7.0 ns (for 117-MHz device)
- 7.5 ns (for 100-MHz device)
- Clock...