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Cypress Semiconductor Electronic Components Datasheet

CY7C1373KV33 Datasheet

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

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CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
18-Mbit (512K × 36/1M × 18) Flow-Through SRAM
with NoBL™ Architecture (With ECC)
18-Mbit (512K × 36/1M × 18) Flow-through SRAM with NoBL™ Architecture (With ECC)
Features
No Bus Latency(NoBL) architecture eliminates dead cycles
between write and read cycles
Supports up to 133-MHz bus operations with zero wait states
Data is transferred on every clock
Pin-compatible and functionally equivalent to ZBT™ devices
Internally self-timed output buffer control to eliminate the need
to use OE
Registered inputs for flow through operation
Byte write capability
3.3 V/2.5 V I/O power supply (VDDQ)
Fast clock-to-output times
6.5 ns (for 133-MHz device)
Clock enable (CEN) pin to enable clock and suspend operation
Synchronous self-timed writes
Asynchronous output enable
Available in JEDEC-standard Pb-free 100-pin TQFP packages
Three chip enables for simple depth expansion
Automatic power-down feature available using ZZ mode or CE
deselect
Burst capability – linear or interleaved burst order
Low standby power
On chip Error Correction Code (ECC) to reduce Soft Error Rate
(SER)
Functional Description
The CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33 are
3.3 V, 512K × 36/1M × 18 synchronous flow through burst SRAM
designed specifically to support unlimited true back-to-back
read/write operations with no wait state insertion. The
CY7C1371KV33/CY7C1371KVE33/CY7C1373KV33
are
equipped with the advanced No Bus Latency (NoBL) logic
required to enable consecutive read/write operations with data
being transferred on every clock cycle. This feature dramatically
improves the throughput of data through the SRAM, especially
in systems that require frequent write-read transitions.
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock input is qualified by the
clock enable (CEN) signal, which when deasserted suspends
operation and extends the previous clock cycle. Maximum
access delay from the clock rise is 6.5 ns (133-MHz device).
Write operations are controlled by the two or four byte write
select (BWX) and a write enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous chip enables (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To avoid bus contention, the
output drivers are synchronously tristated during the data portion
of a write sequence.
Selection Guide
Maximum access time
Maximum operating current
Description
133 MHz 100 MHz Unit
6.5 8.5 ns
× 18 129
114 mA
× 36 149
134 mA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97852 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 1, 2016


Cypress Semiconductor Electronic Components Datasheet

CY7C1373KV33 Datasheet

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

No Preview Available !

CY7C1371KV33
CY7C1371KVE33
CY7C1373KV33
Logic Block Diagram – CY7C1371KV33
A0, A1, A
MODE
CLK C
CEN
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
BURST
LOGIC
Q1
Q0
A1'
A0'
ADV/LD
BW A
BW B
BW C
BW D
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQP A
DQP B
DQP C
DQP D
Logic Block Diagram – CY7C1371KVE33
CLK
/CEN
A0, A1, A
MODE
C /CE
ADV or /LD
/BWA
/BWB
/BWC
/BWD
/WE
ADDRESS
REGISTER
ADV or /LD
C
A1 D1
Q1 A1'
A0 D0
Q0 A0'
BURST LOGIC
WRITE ADDRESS
REGISTER
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S ECC
E DECODER
A
M
P
S
D
A
T
A
S
T
E
E
R
I
N
G
O
U
T
P
U
T
B
U
F
F
E
R
S
DQS
DQPA
DQPB
DQPC
DQPD
E
/OE READ
LOGIC
/CE1
CE2
/CE1
ZZ
SLEEP
CONTROL
ECC
ENCODER
INPUT
REGISTER
E
Document Number: 001-97852 Rev. *E
Page 2 of 24


Part Number CY7C1373KV33
Description 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM
Maker Cypress Semiconductor
Total Page 24 Pages
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