CY7C141

Manufacturer: Cypress (now Infineon)

CY7C141 datasheet by Cypress (now Infineon).

This datasheet includes multiple variants, all published together in a single manufacturer document.

CY7C141 Datasheet Details

Two ports are provided permitting independent access to any location in memory. The CY7C130/130A/ CY7C131/131A can be used as either a.

True dual-ported memory cells, which allow simultaneous reads of the same memory location
1K x 8 organization
0.65 micron CMOS for optimum speed and power
High speed access: 15 ns
Low operating power: ICC = 110 mA (maximum)
Fully asynchronous operation
Automatic power down
BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on CY7C140/CY7C141
INT flag for port-to-port munication
Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC, 52-pin TQFP

Part Number	Description
CY7C1410AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410JV18	(CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18	(CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C1411AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18	(CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18	(CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411KV18	36-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1412AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1412JV18	SRAM 2-Word Burst Architecture
CY7C1412KV18	36-Mbit QDR II SRAM Two-Word Burst Architecture