CY7C1410AV18 Datasheet (cy7c14xxav18) 36-mbit Qdr-ii Sram 2-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II™ SRAM 2-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1410AV18
Manufacturer	Cypress (now Infineon)
File Size	1.19 MB
Description	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
Datasheet	CY7C1410AV18 CY7C1412AV18 Datasheet (PDF)

The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture.

QDR-II architecture consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations.

Separate Independent Read and Write data ports.
Supports concurrent transactions.
250-MHz clock for high bandwidth.
2-Word Burst on all accesses.
Double Data Rate (DDR) interfaces on both Read and Write www. DataSheet4U. com ports (data transferred at 500 MHz) @ 250 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight-.

Part Number	Description
CY7C1410JV18	(CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18	(CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C141	1K x 8 Dual-Port Static RAM
CY7C1411AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18	(CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18	(CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411KV18	36-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1412AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1412JV18	SRAM 2-Word Burst Architecture
CY7C1412KV18	36-Mbit QDR II SRAM Two-Word Burst Architecture