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CY7C141 Datasheet 1k X 8 Dual-port Static Ram

Manufacturer: Cypress (now Infineon)

Overview: CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141 are high speed CMOS 1K by 8 dual-port static RAMs.

Two ports are provided permitting independent access to any location in memory.

The CY7C130/130A/ CY7C131/131A can be used as either a s

Key Features

  • True dual-ported memory cells, which allow simultaneous reads of the same memory location.
  • 1K x 8 organization.
  • 0.65 micron CMOS for optimum speed and power.
  • High speed access: 15 ns.
  • Low operating power: ICC = 110 mA (maximum).
  • Fully asynchronous operation.
  • Automatic power down.
  • Master CY7C130/130A/CY7C131/131A easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141.
  • BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on C.

More Datasheets from Cypress (now Infineon)

Part Number Description
CY7C1410AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410JV18 (CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18 (CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C1411AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18 (CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18 (CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411KV18 36-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1412AV18 (CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1412JV18 SRAM 2-Word Burst Architecture
CY7C1412KV18 36-Mbit QDR II SRAM Two-Word Burst Architecture

CY7C141 Distributor