CY7C1410JV18 Datasheet (cy7c14xxjv18) Sram 2-word Burst Architecture

Manufacturer: Cypress (now Infineon)

Overview: CY7C1410JV18, CY7C1425JV18 CY7C1412JV18, CY7C1414JV18 36-Mbit QDR™-II SRAM 2-Word Burst.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Datasheet Details

Part number	CY7C1410JV18
Manufacturer	Cypress (now Infineon)
File Size	682.68 KB
Description	(CY7C14xxJV18) SRAM 2-Word Burst Architecture
Datasheet	CY7C1410JV18 CY7C1412JV18 Datasheet (PDF)

The CY7C1410JV18, CY7C1425JV18, CY7C1412JV18, and CY7C1414JV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture.

QDR-II architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has data outputs to support read operations and the write port has data inputs to support write operations.

Configurations CY7C1410JV18.
4M x 8 CY7C1425JV18.
4M x 9 CY7C1412JV18.
2M x 18 CY7C1414JV18.
1M x 36 Separate independent read and write data ports.
Supports concurrent transactions 267 MHz clock for high bandwidth 2-word burst on all accesses (data transferred at 534 MHz) at 267 MHz.
Double Data Rate (DDR) interfaces on both read and write ports www. DataSheet4U. com.
Functional.

Part Number	Description
CY7C1410AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1410V18	(CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C141	1K x 8 Dual-Port Static RAM
CY7C1411AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18	(CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411JV18	(CY7C14xxJV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411KV18	36-Mbit QDR II SRAM Four-Word Burst Architecture
CY7C1412AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture
CY7C1412JV18	SRAM 2-Word Burst Architecture
CY7C1412KV18	36-Mbit QDR II SRAM Two-Word Burst Architecture