CY7C1410AV18 Datasheet ((CY7C14xxAV18) 36-Mbit QDR-II SRAM 2-Word Burst Architecture)

Part: CY7C1410AV18
Manufacturer: Cypress (official site)
Size: 1.19 MB

CY7C1410AV18 Key Features

Separate Independent Read and Write data ports
Supports concurrent transactions
250-MHz clock for high bandwidth
2-Word Burst on all accesses
Double Data Rate (DDR) interfaces on both Read and Write .. ports (data transferred at 500 MHz) @ 250 MHz
Two input clocks (K and K) for precise DDR timing
SRAM uses rising edges only
Two input clocks for output data (C and C) to minimize clock skew and flight-time mismatches
Echo clocks (CQ and CQ) simplify data capture in high-speed systems
Single multiplexed address input bus latches address inputs for both Read and Write ports

Related Cypress Datasheets

Part Number	Description
CY7C1410JV18	(CY7C14xxJV18) SRAM 2-Word Burst Architecture
CY7C1410V18	(CY7C14xxV18) SRAM 2-Word Burst Architecture
CY7C141	1K x 8 Dual-Port Static RAM
CY7C1411AV18	(CY7C14xxAV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture
CY7C1411BV18	(CY7C14xxBV18) 36-Mbit QDR-II SRAM 4-Word Burst Architecture

CY7C1410AV18 Description

QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to pletely eliminate the need to “turn-around” the data bus required with mon IO devices.