CY7C1413KV18 Features
* Separate independent read and write data ports
* Supports concurrent transactions
* 333 MHz clock for high bandwidth
* Four-word burst for reducing address bus frequency
* Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
CY7C1411KV18-CypressSemiconductor.pdf
Datasheet Details
CY7C1413KV18, CY7C1411KV18
Cypress Semiconductor
1.28 MB
36-mbit qdr ii sram four-word burst architecture.
This datasheet PDF includes multiple part numbers: CY7C1413KV18, CY7C1411KV18.
Please refer to the document for exact specifications by model.
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CY7C1413KV18 Distributor
