CY7C1527V18 - 1.8V Synchronous Pipelined SRAM

This page provides the datasheet information for the CY7C1527V18, a member of the CY7C1516V18 1.8V Synchronous Pipelined SRAM family.

Product Overview

Cypress Semiconductor

Part number	CY7C1527V18
Manufacturer	Cypress Semiconductor
File Size	400.92 KB
Description	1.8V Synchronous Pipelined SRAM
Datasheet	CY7C1527V18 Datasheet
Additional preview pages of the CY7C1527V18 datasheet.

72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36).
300 MHz clock for high bandwidth.
2-word burst for reducing address bus frequency.
Double Data Rate (DDR) interfaces (data transferred at 600 MHz) at 300 MHz.
Two input clocks (K and K) for precise DDR timing.
SRAM uses rising edges only.
Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches.
Echo clocks (CQ and CQ) simplify data capture in high-speed systems.

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Published: Nov 6, 2016 |