* Configurations With Read Cycle Latency of 2.5 cycles: CY7C2561KV18
* 8M x 8 CY7C2576KV18
* 8M x 9 CY7C2563KV18
* 4M x 18 CY7C2565KV18
* 2M x 36 Separate independent read and write data ports
* Supports concurrent transactions 550 MHz clock for high bandwid
CY7C2565KV18 Datasheet (915.19 KB)
CY7C2565KV18
Cypress Semiconductor
915.19 KB
72-mbit qdr-ii sram 4-word burst architecture.
www.DataSheet.co.kr PRELIMINARY CY7C2561KV18, CY7C2576KV18 CY7C2563KV18, CY7C2565KV18 72-Mbit QDR™-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Re.
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