CY7C2642KV18 Overview
CY7C2642KV18/CY7C2644KV18 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT 144-Mbit QDR® II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) with ODT.
CY7C2642KV18 Key Features
- Separate independent read and write data ports
- Supports concurrent transactions
- 333-MHz clock for high bandwidth
- Two-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces on both read and write ports
- Available in 2.0-clock cycle latency
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Echo clocks (CQ and CQ) simplify data capture in high-speed
- Data valid pin (QVLD) to indicate valid data on the output