PSoC4500S
Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
Key Features
- 48-MHz Arm Cortex-M0+ CPU with single-cycle multiply
- Up to 256 KB of flash with Read Accelerator
- Up to 32 KB of SRAM
- 8-channel DMA engine
- Two Divide and Square Root computation accelerators Programmable Analog
- Four opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
- Two 12-bit 1-Msps SAR ADCs with differential and single-ended modes, and Channel Sequencer with signal averaging. Simultaneous sampling is provided.
- Single-slope 10-bit ADC function provided by a capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode Programmable Digital
