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Diodes Semiconductor Electronic Components Datasheet

DMP1018UCB9 Datasheet

P-CHANNEL ENHANCEMENT MODE MOSFET

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Product Summary
VDSS
-12V
RDS(on)
12m
Qg
4.9nC
Qgd
1.1nC
ID
-7.6A
Typ. @ VGS = -4.5V, TA = +25°C
Description
This 1st generation Lateral MOSFET (LD-MOS) is engineered to
minimize on-state losses and switch ultra-fast, making it ideal for high
efficiency power transfer. Using Chip-Scale Package (CSP) to
increase power density by combining low thermal impedance with
minimal RDS(on) per footprint area.
Applications
DC-DC Converters
Battery Management
Load Switch
DMP1018UCB9
P-CHANNEL ENHANCEMENT MODE MOSFET
Features
LD-MOS technology with the lowest Figure of Merit:
RDS(on) = 12mto Minimize On-State Losses
Qg = 4.9nC for Ultra-Fast Switching
Vgs(th) = -0.8V typ. for a Low Turn-On Potential
CSP with Footprint 1.5mm × 1.5mm
Height = 0.62mm for Low Profile
ESD = 3kV HBM Protection of Gate
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Qualified to AEC-Q101 Standards for High Reliability
Mechanical Data
Case: U-WLB1515-9
Terminal Connections: See Diagram Below
GSS
ESD PROTECTED TO 3kV
S SS
D DD
Top-View
Pin Configuration
Equivalent Circuit
Ordering Information (Note 3)
Notes:
Part Number
DMP1018UCB9-7
Case
U-WLB1515-9
Packaging
3,000/Tape & Reel
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. For packaging details, go to our website at http://www.diodes.com/products/packages.html.
Marking Information
EW
YM
EW = Product Type Marking Code
YM = Date Code Marking
Y or Y = Year (ex: B = 2014)
M or M = Month (ex: 9 = September)
Date Code Key
Year
Code
Month
Code
2012
Z
Jan
1
Feb
2
DMP1018UCB9
Document number: DS36149 Rev. 3 - 2
2013
A
Mar
3
2014
B
Apr May
45
2015
C
Jun Jul
67
1 of 6
www.diodes.com
2016
D
Aug
8
Sep
9
2017
E
Oct
O
2018
F
Nov Dec
ND
November 2014
© Diodes Incorporated


Diodes Semiconductor Electronic Components Datasheet

DMP1018UCB9 Datasheet

P-CHANNEL ENHANCEMENT MODE MOSFET

No Preview Available !

Maximum Ratings (@TA = +25°C, unless otherwise specified.)
Characteristic
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (Note 5) VGS = -4.5V
Steady
State
Continuous Drain Current (Note 6) VGS = -4.5V
Steady
State
Pulsed Drain Current (Pulse duration 10μs, duty cycle 1%)
TA = +25°C
TA = +70°C
TA = +25°C
TA = +70°C
Symbol
VDSS
VGSS
ID
ID
IDM
DMP1018UCB9
Value
-12
-6
-7.6
-6.0
-5.5
-4.3
-60
Units
V
V
A
A
A
Thermal Characteristics (@TA = +25°C, unless otherwise specified.)
Characteristic
Total Power Dissipation (Note 5)
Total Power Dissipation (Note 6)
Thermal Resistance, Junction to Ambient (Note 5)
Thermal Resistance, Junction to Ambient (Note 6)
Operating and Storage Temperature Range
Symbol
PD
PD
RθJA
RθJA
TJ, TSTG
Value
1.0
1.8
126.8
69
-55 to +150
Units
W
W
°C/W
°C/W
°C
Electrical Characteristics (@TA = +25°C, unless otherwise specified.)
Characteristic
OFF CHARACTERISTICS (Note 7)
Drain-Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate-Source Leakage
ON CHARACTERISTICS (Note 7)
Gate Threshold Voltage
@TC = +25°C
Static Drain-Source On-Resistance
Forward Transfer Admittance
Diode Forward Voltage (Note 6)
Reverse Recovery Charge
Reverse Recovery Time
DYNAMIC CHARACTERISTICS (Note 8)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Series Gate Resistance
Total Gate Charge (4.5V)
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Symbol
BVDSS
IDSS
IGSS
VGS(th)
RDS (ON)
|Yfs|
VSD
Qrr
trr
Ciss
Coss
Crss
RG
Qg
Qgs
Qgd
tD(on)
tr
tD(off)
tf
Min
-12
-0.4
Typ
-0.8
12
15
5.5
-0.7
30.2
71.4
457
272
120
21.23
4.9
0.6
1.1
4.45
12
100
93
Notes:
5. Device mounted on FR-4 PCB with minimum recommended pad layout.
6. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz (0.071-mm thick) Cu.
7. Short duration pulse test used to minimize self-heating effect.
8. Guaranteed by design. Not subject to production testing.
Max
-1
-100
-1.3
18
22
-1
Unit Test Condition
V VGS = 0V, ID = -250μA
μA VDS = -9.6V, VGS = 0V
nA VGS = -6.0V, VDS = 0V
V VDS = VGS, ID = -250μA
m
VGS = -4.5V, ID = -2A
VGS = -2.5V, ID = -2A
S VDS = -6V, ID = -2A
V VGS = 0V, IS = -2A
nC Vdd = -5V, IF = -2A,
ns di/dt = 200A/μs
pF
pF
pF
VDS = -6V, VGS = 0V,
f = 1.0MHz
VDS = 0V, VGS = 0V, f = 1.0MHz
nC
nC
nC
VGS = -4.5V, VDS = -6V,
ID = -2A
ns
ns VDD = -6V, VGS = -4.5V,
ns IDS = -2A, RG = 2,
ns
DMP1018UCB9
Document number: DS36149 Rev. 3 - 2
2 of 6
www.diodes.com
November 2014
© Diodes Incorporated


Part Number DMP1018UCB9
Description P-CHANNEL ENHANCEMENT MODE MOSFET
Maker Diodes
Total Page 6 Pages
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