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M13S64164A-5TG - 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

Key Features

  • z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe.

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Other Datasheets by ESMT (Elite Semiconductor Microelectronics Technology)

Part Number Description
M13S64164A-5TG2C 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5TG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5BG 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-5BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM
M13S64164A-4BG2Y 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

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ESMT M13S64164A DDR SDRAM 1M x 16 Bit x 4 Banks Double Data Rate SDRAM Features z JEDEC Standard z Internal pipelined double-data-rate architecture, two data access per clock cycle z Bi-directional data strobe (DQS) z On-chip DLL z Differential clock inputs (CLK and CLK ) z DLL aligns DQ and DQS transition with CLK transition z Quad bank operation z CAS Latency : 2, 2.5, 3 z Burst Type : Sequential and Interleave z Burst Length : 2, 4, 8 z All inputs except data & DM are sampled at the rising edge of the system clock(CLK) z Data I/O transitions on both edges of data strobe (DQS) z DQS is edge-aligned with data for reads; center-aligned with data for WRITE z Data mask (DM) for write masking only z VDD = 2.3V ~ 2.7V, VDDQ = 2.3V ~ 2.