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M15F2G16128A-BDBG2F Datasheet 16m X 16 Bit X 8 Banks Ddr Iii Sdram

Manufacturer: ESMT (Elite Semiconductor Microelectronics Technology)

Overview: ESMT DDR III SDRAM Feature z 1.5V ± 0.075V (JEDEC Standard Power Supply) z Programmable CAS　Latency: 5, 6, 7, 8, 9, 10 and 11 z 8 Internal memory banks (BA0- BA2) z Differential clock input (CK, CK ) z CAS WRITE Latency (CWL): 5,6,7,8,9 z POSTED CAS ADDITIVE Programmable Additive Latency (AL): 0, CL-1, CL-2 clock z Programmable Sequential / Interleave Burst Type z Through ZQ pin (RZQ:240 ohm±1%) z Programmable Burst Length: 4, 8 M15F2G16128A (2F) 16M x 16 Bit x 8 Banks DDR III SDRAM z 8n-bit prefetch architecture z Output Driver Impedance Control z Differential bidirectional data strobe z Internal(self) calibration:Internal self calibration z OCD Calibration z Dynamic ODT (Rtt_Nom & Rtt_WR) z Auto Self-Refresh z Self-Refresh Temperature z RoHS pliance Ordering Information Product ID Max Freq. VDD Data Rate (CL-tRCD-tRP) Package ments M15F2G16128A –BDBG2F 800MHz 1.5V DDR3-1600 (11-11-11) 96 ball BGA Pb-free Elite Semiconductor Memory Technology Inc Publication Date : Jul. 2013 Revision : 1.

General Description

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.

It is internally configured as an eight bank DRAMs.

The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices.

Key Features

  • and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK 　falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages. Elite Semiconductor Memory Technology Inc Publication Date : Jul. 2013 Revision : 1.0.

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