UPD4564441 Datasheet | Elpida Memory

DATA SHEET MOS INTEGRATED CIRCUIT µPD4564441, 4564841, 4564163 64M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 × 4 × 4, 2,097,152 × 8 × 4, 1,048,576 ×16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock. The synchronous DRAMs are patible with Low Voltage TTL (LVTTL). These products are packaged in 54-pin TSOP (II). Features - Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge - Pulsed interface - Possible to assert random column address in every cycle - Quad internal banks controlled by A12 and A13 (Bank Select) - Byte control (×16) by LDQM and UDQM - Programmable Wrap sequence (Sequential / Interleave) - Programmable burst length (1, 2, 4, 8 and full page) - Programmable /CAS latency (2 and 3) - Automatic precharge and controlled precharge - CBR (auto) refresh and self refresh - ×4, ×8, ×16 organization - Single 3.3 V ± 0.3 V power supply - LVTTL patible inputs and outputs - 4,096 refresh cycles / 64 ms - Burst termination by Burst stop mand and Precharge mand The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information. Document No. E0149N10 (Ver.1.0) (Previous No. M12621EJCV0DS00) Date Published August 2001 (K) Printed in Japan Elpida Memory, Inc. is a joint venture DRAM pany of NEC Corporation and Hitachi, Ltd. µPD4564441, 4564841, 4564163 Ordering Information Part number Organization (word × bit × bank) 4M × 4 × 4 Clock frequency MHz (MAX.) 125 100 100 2M × 8 × 4 125 100 100 1M × 16 × 4 125 100 100...