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EM484M1644VTA Datasheet 64mb Sdram

Manufacturer: Eorex

Overview: .. 64Mb SDRAM Ordering Information EM 48 2M 32 4 4 V T A – 5 L EOREX Logo EDO/FPM D-RAMBUS DDRSDRAM DDRSGRAM SGRAM SDRAM : : : : : : 40 41 42 43 46 48 F: PB free package Power Blank : Standard L : Low power I : Industrial Density 16M : 16 Mega Bits 8M : 8 Mega Bits 4M : 4 Mega Bits 2M : 2 Mega Bits 1M : 1 Mega Bit Organization 8 : x8 9 : x9 16 : x16 18 : x18 32 : x32 Refresh 1 : 1K, 8 : 8K 2 : 2K, 6 :16K 4 : 4K Bank 2 : 2Bank 6 : 16Bank 4 : 4Bank 3 : 32Bank 8 : 8Bank Min Cycle Time ( Max Freq.) -5 : 5ns ( 200MHz ) -6 : 5ns ( 167MHz ) -7 : 7ns ( 143MHz ) -75 : 7.5ns ( 133MHz ) -8 : 8ns ( 125MHz ) -10 : 10ns ( 100MHz ) Revision A : 1st B : 2nd C : 3rd D :4th G: for VGA version only Interface V: 3.3V R: 2.5V Package C: CSP B: uBGA T: TSOP Q: TQFP P: PQFP ( QFP ) L: LQFP URL: http://.eorex. Email: sales@eorex. Rev.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

The EM482M3244VTA is Synchronous Dynamic Random Access Memory ( SDRAM ) organized as 524,288 words x 4 banks x 32 bits.

All inputs and outputs are synchronized with the positive edge of the clock .

The 64Mb SDRAM uses synchronized pipelined architecture to achieve high speed data transfer rates and is designed to operate in 3.3V low power memory system.

Key Features

  • Fully synchronous to positive clock edge.
  • Single 3.3V +/- 0.3V power supply.
  • LVTTL compatible with multiplexed address.
  • Programmable Burst Length ( B/ L ) - 1,2,4,8 or full page.
  • Programmable CAS Latency ( C/ L ) - 2 or 3.
  • Data Mask ( DQM ) for Read/Write masking.
  • Programmable wrap sequential - Sequential ( B/ L = 1/2/4/8/full page ) - Interleave ( B/ L = 1/2/4/8 ).
  • Burst read with single-bit write operation.
  • All i.

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