Clock rate: 133/125/100 MHz Fully synchronous operation Internal pipelined architecture Four internal banks (1M x 32bit x 4bank) Programmable Mode - CAS# Latency: 1, 2 & .

Symbol Type Description CLK 4M x 32 HH LPSDRAM EM66932A Table 1. Pin Details of 4Mx32 HH LPSDRAM Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal bu.

EM669325

EM6603

EM6604

EM6605

EM6607

EM6617

EM6620

EM6621

EM6622

EM6625

EM6626

EM6635

EM6640