EP520 Overview
The EP520 SDRAM controller interfaces between a processor or DMA device with an SDRAM. It performs SDRAM read and write access based on processor or DMA requests. SDRAM timing such as row and column latency, precharge timing, and row access length are automatically handled by the SDRAM controller.
EP520 Key Features
- Supports Virtex™, Virtex™-E, and Spartan™-II FPGAs Supports industry standard SDRAM and PC100 SDRAM DIMM. Supports regis