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Exar Corporation

XRT73L04A Datasheet Preview

XRT73L04A Datasheet

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

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XRT73L04A
OCTOBER 2003
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
GENERAL DESCRIPTION
The XRT73L04A, 4-Channel, DS3/E3/STS-1 Line In-
terface Unit is an improved version of the XRT73L04
and consists of four independent line transmitters and
receivers integrated on a single chip designed for
DS3, E3 or SONET STS-1 applications.
Each channel of the XRT73L04A can be configured
to support the E3 (34.368 Mbps), DS3 (44.736 Mbps)
or the SONET STS-1 (51.84 Mbps) rates. Each
channel can be configured to operate in a mode/data
rate that is independent of the other channels.
In the transmit direction, each channel encodes input
data to either B3ZS (DS3/STS-1) or HDB3 (E3) for-
mat and converts the data into the appropriate pulse
shapes for transmission over coaxial cable via a 1:1
transformer.
In the receive direction, the XRT73L04A performs
equalization on incoming signals, performs Clock Re-
covery, decodes data from either B3ZS or HDB3 for-
mat, converts the receive data into TTL/CMOS for-
mat, checks for LOS or LOL conditions and detects
and declares the occurrence of Line Code Violations.
FEATURES
Incorporates an improved Timing Recovery circuit
and is pin and functional compatible to XRT73L04
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Contains a 4-Wire Microprocessor Serial Interface
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Uses Minimum External components
Single +3.3V Power Supply
5V tolerant I/O
-40°C to +85°C Operating Temperature Range
Available in a Thermally Enhanced 144 pin TQFP
package
APPLICATIONS
Digital Cross Connect Systems
CSU/DSU Equipment
Routers
Fiber Optic Terminals
Multiplexers
ATM Switches
FIGURE 1. XRT73L04A BLOCK DIAGRAM
E3_(n) STS-1/DS3_(n)
Host/(HW) RLOL_(n) EXClk_(n) RxOFF
RxClkINV
RTIP_(n)
RRing_(n)
REQEN_(n)
LOSTHR
SDI
SDO
SClk
CS/(SR/DR)
REGR
AGC/
Equalizer
Peak
Detector
Slicer
Clock
Recovery
LOS Detector
Serial
Processor
Interface
Loop MUX
Data
Recovery
Invert
HDB3/
B3ZS
Decoder
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Transmit
Logic
Duty Cycle Adjust
MTIP_(n)
MRing_(n)
DMO_(n)
Device
Monitor
Tx
Control
Channel 0
Channel 1
Channel 2
Channel 3
Notes: 1. (n) = 0, 1, 2 , or 3 for respective Channels
2. Serial Processor Interface input pins are shared by the four Channels in HOST Mode and redefined in
Hardware Mode.
RxClk_(n)
RPOS_(n)
RNEG_(n)/
(LCV_(n))
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
TxLEV_(n)
TxOFF
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com




Exar Corporation

XRT73L04A Datasheet Preview

XRT73L04A Datasheet

4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT

No Preview Available !

XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
TYPICAL APPLICATIONS
FIGURE 2. MULTICHANNEL ATM APPLICATION
ATM
S w itc h /
SAR
RPOS
RNEG
R xLin eC lk
RRPOS
RRNEG
RRClk
RPOS
RNEG
R xC lk
RPOS
RNEG
RxClk
RTIP
R R in g
XRT72L74
TPOS
TNEG
T xLin eC lk
4 Channel DS3 ATM UNI
XRT71D04
MClk
4 Channel E3/DS3 J/A
XRT73L04A
TPOS
TNEG
TxClk
TTIP
TRing
4 Channel E3/DS3 LIU
FIGURE 3. MULTISERVICE - FRAME RELAY APPLICATION
F ram e
Relay
RPOS
RNEG
RxLineClk
RRPOS
RRNEG
RRClk
RPOS
RNEG
RxClk
RPOS
RNEG
RxClk
RTIP
RRing
XRT72L58
TPOS
TNEG
TxLineClk
XRT71D04
MClk
XRT73L04A
TPOS
TNEG
TxClk
TTIP
TRing
8 Channel E3/DS3 Framer 2 x 4 Channel E3/DS3 J/A 2 x 4 Channel E3/DS3 LIU
TRANSMIT INTERFACE CHARACTERISTICS:
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
from the line
Integrated Pulse Shaping Circuit
Built-in B3ZS/HDB3 Encoder (which can be dis-
abled)
Contains Transmit Clock Duty Cycle Correction Cir-
cuit on-chip
Generates pulses that comply with the ITU-T G.703
pulse template (E3 applications)
Generates pulses that comply with the DSX-3 pulse
template as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993
Generates pulses that comply with the STSX-1
pulse template as specified in Bellcore GR-253-
CORE
Transmitter can be turned off in order to support
redundancy designs
RECEIVE INTERFACE CHARACTERISTICS:
Integrated Adaptive Receive Equalization (optional)
and Timing Recovery
Declares and Clears the LOS defect per ITU-T
G.775 requirements (E3 and DS3 applications)
Meets Jitter Tolerance Requirements as specified in
ITU-T G.823_1993 (E3 Applications)
Meets Jitter Tolerance Requirements as specified in
Bellcore GR-499-CORE (DS3 Applications)
Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms
Built-in B3ZS/HDB3 Decoder (which can be dis-
abled)
Recovered Data can be muted while the LOS Con-
dition is declared
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment
Receiver can be powered down in order to con-
serve power in redundancy designs
2


Part Number XRT73L04A
Description 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
Maker Exar Corporation
Total Page 30 Pages
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