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Freescale Semiconductor Data Sheet:
Document Number: MSC8144E Rev. 14, 5/2010
MSC8144E
Quad Core Digital Signal Processor
FC-PBGA–783 29 mm × 29 mm
• Four StarCore® SC3400 DSP subsystems, each with an SC3400 DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache, memory management unit (MMU), extended programmable interrupt controller (EPIC), two general-purpose 32-bit timers, debug and profiling support, and low-power Wait and Stop processing modes.
• Chip-level arbitration and system (CLASS) that provides full fabric non-blocking arbitration between the processing elements and other initiators and the M2 memory, DDR SRAM controller, device configuration control and status registers, and other targets.
• 128 Kbyte L2 shared instruction cache.
MSC8144E Datasheet
