GS88136T srams equivalent, (gs88118 / gs88136t) sync burst srams.
* FT pin for user-configurable flow through or pipelined operation
* Single Cycle Deselect (SCD) Operation
* IEEE 1149.1 JTAG-compatible Boundary Scan
* O.
* 100-lead TQFP package -11 -11.5 -100 -80 -66 10 ns 10 ns 12.5 ns 15 ns Pipeline tCycle 10 ns 4.0 ns 4.0 ns 4.0 ns .
Applications
The GS88118//36T is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds appli.
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