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GS81314PD19GK Datasheet Preview

GS81314PD19GK Datasheet

144Mb SigmaQuad-IVe Burst of 4 Single-Bank ECCRAM

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GS81314PD19/37GK-933/800
260-Pin BGA
Com & Ind Temp
POD I/O
144Mb SigmaQuad-IVe™
Burst of 4 Single-Bank ECCRAM™
Up to 933 MHz
1.2V ~ 1.3V VDD
1.2V ~ 1.3V VDDQ
Features
• 4Mb x 36 and 8Mb x 18 organizations available
• Organized as a single logical memory bank
• 933 MHz maximum operating frequency
• 933 MT/s peak transaction rate (in millions per second)
• 134 Gb/s peak data bandwidth (in x36 devices)
• Separate I/O DDR Data Buses
• Non-multiplexed SDR Address Bus
• One operation - Read or Write - per clock cycle
• No address/bank restrictions on Read and Write ops
• Burst of 4 Read and Write operations
• 5 cycle Read Latency
• On-chip ECC with virtually zero SER
• Loopback signal timing training capability
• 1.2V ~ 1.3V nominal core voltage
• 1.2V ~ 1.3V POD I/O interface
• Configuration registers
• Configurable ODT (on-die termination)
• ZQ pin for programmable driver impedance
• ZT pin for programmable ODT impedance
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 RoHS-
compliant BGA package
SigmaQuad-IVeFamily Overview
SigmaQuad-IVe ECCRAMs are the Separate I/O half of the
SigmaQuad-IVe/SigmaDDR-IVe family of high performance
ECCRAMs. Although similar to GSI's third generation of
networking SRAMs (the SigmaQuad-IIIe/SigmaDDR-IIIe
family), these fourth generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS81314PD19/37GK SigmaQuad-IVe ECCRAMs are
synchronous devices. They employ three pairs of positive and
negative input clocks; one pair of master clocks, CK and CK,
and two pairs of write data clocks, KD[1:0] and KD[1:0]. All
six input clocks are single-ended; that is, each is received by a
dedicated input buffer.
CK and CK are used to latch address and control inputs, and to
control all output timing. KD[1:0] and KD[1:0] are used solely
to latch data inputs.
Each internal read and write operation in a SigmaQuad-IVe B4
ECCRAM is four times wider than the device I/O bus. An
input data bus de-multiplexer is used to accumulate incoming
data before it is simultaneously written to the memory array.
An output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaQuad-IVe B4 ECCRAM is always two address
pins less than the advertised index depth (e.g. the 8M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by SER events such as cosmic rays, alpha particles,
etc. The resulting Soft Error Rate of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no on-chip ECC,
which typically have an SER of 200 FITs/Mb or more.
All quoted SER values are at sea level in New York City.
Speed Grade
-933
-800
Parameter Synopsis
Max Operating Frequency
933 MHz
800 MHz
Read Latency
5 cycles
5 cycles
VDD
1.25V to 1.35V
1.15V to 1.35V
Rev: 1.02 3/2016
1/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology




GSI Technology

GS81314PD19GK Datasheet Preview

GS81314PD19GK Datasheet

144Mb SigmaQuad-IVe Burst of 4 Single-Bank ECCRAM

No Preview Available !

GS81314PD19/37GK-933/800
8M x 18 Pinout (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
VDD NUO VDD
NUI
NC
(RSVD)
MCH
(CFG)
MRW
ZQ
PZT1 DINV0 VDD QINV0 VDD
B
VSS NUO VSS
NUI
MCL
MCH
(B4M)
NC
(RSVD)
MCH
(SIOM)
PZT0
D0
VSS Q0
VSS
C Q17 VDDQ D17 VDDQ VSS SA13 VDD SA14 VSS VDDQ NUI VDDQ NUO
D
VSS NUO VSS
NUI
SA19
VDDQ
NC
(288 Mb)
VDDQ
SA20
D1
VSS
Q1
VSS
E Q16 VDDQ D16 VDD VSS SA11 VSS SA12 VSS VDD NUI VDDQ NUO
F
VSS NUO VSS
NUI SA17 VDD VDDQ VDD SA18
D2
VSS Q2 VSS
G Q15 NUO D15 NUI VSS SA9 NUI SA10 VSS D3 NUI Q3 NUO
H Q14 VDDQ D14 VDDQ SA15 VDDQ W VDDQ SA16 VDDQ NUI VDDQ NUO
J VSS NUO VSS NUI VSS SA7 VSS SA8 VSS D4 VSS Q4 VSS
K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0
L CQ1 VSS QVLD1 Vss KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0
M VSS Q13 VSS D13 VSS SA5 VSS SA6 VSS NUI VSS NUO VSS
N NUO VDDQ NUI VDDQ PLL VDDQ R VDDQ MCL VDDQ D5 VDDQ Q5
P NUO Q12 NUI D12 VSS SA3 MZT SA4 VSS NUI D6 NUO Q6
R VSS Q11 VSS D11 MCH VDD VDDQ VDD RST NUI VSS NUO VSS
T NUO VDDQ NUI VDD VSS SA1 VSS SA2 VSS VDD D7 VDDQ Q7
U
VSS
Q10
VSS
D10
NC
(576 Mb)
VDDQ
NC
(RSVD)
VDDQ
NC
(1152 Mb)
NUI
VSS NUO
VSS
V
NUO VDDQ NUI VDDQ VSS
SA21
(x18)
VDD
NUI
(B2)
VSS VDDQ D8 VDDQ Q8
W VSS Q9 VSS D9 TCK MCL RCS MCL TMS NUI VSS NUO VSS
Y
VDD QINV1 VDD DINV1 TDO
NU
NC
(RSVD)
MCL
TDI
NUI
VDD NUO VDD
Notes:
1. Pins 5B, 6W, 8W, 8Y, and 9N must be tied Low in this device.
2. Pin 5R must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 6B is defined as mode pin B4M in the pinout standard. It must be tied High in this device to select Burst-of-4 configuration.
5. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied High in this device to select Separate I/O configuration.
6. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
7. Pin 8V is defined as address pin SA for B2 devices. It is unused in this device, and must be left unconnected or driven High.
8. Pin 7D is reserved as address pin SA for 288 Mb devices. It is a true no connect in this device.
9. Pin 5U is reserved as address pin SA for 576 Mb devices. It is a true no connect in this device.
10. Pin 9U is reserved as address pin SA for 1152 Mb devices. It is a true no connect in this device.
Rev: 1.02 3/2016
2/39
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2015, GSI Technology


Part Number GS81314PD19GK
Description 144Mb SigmaQuad-IVe Burst of 4 Single-Bank ECCRAM
Maker GSI Technology
Total Page 30 Pages
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