GS81314PQ36GK Datasheet | GSI Technology

GS81314PQ18/36GK-133/120/106 260-Pin BGA & Ind Temp POD I/O 144Mb Sigma Quad-IVe™ Burst of 2 Multi-Bank ECCRAM™ Up to 1333 MHz 1.25V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ Features - 4Mb x 36 and 8Mb x 18 organizations available - Organized as 16 logical memory banks - 1333 MHz maximum operating frequency - 2.666 BT/s peak transaction rate (in billions per second) - 192 Gb/s peak data bandwidth (in x36 devices) - Separate I/O DDR Data Buses - Non-multiplexed DDR Address Bus - Two operations - Read and Write - per clock cycle - Certain address/bank restrictions on Read and Write ops - Burst of 2 Read and Write operations - 6 cycle Read Latency - On-chip ECC with virtually zero SER - Loopback signal timing training capability - 1.25V ~ 1.3V nominal core voltage - 1.2V ~ 1.3V POD I/O interface - Configuration registers - Configurable ODT (on-die termination) - ZQ pin for programmable driver impedance - ZT pin for programmable ODT impedance - IEEE 1149.1 JTAG-pliant Boundary Scan - 260-pin, 14 mm x 22 mm, 1 mm ball pitch, 6/6 Ro HS- pliant BGA package Sigma Quad-IVe™ Family Overview Sigma Quad-IVe ECCRAMs are the Separate I/O half of the Sigma Quad-IVe/Sigma DDR-IVe family of high performance ECCRAMs. Although similar to GSI's third generation of networking SRAMs (the Sigma Quad-IIIe/Sigma DDR-IIIe family), these fourth generation devices offer several new Features that help enable significantly higher...