Description
Symbol
Description
SA[21:1] D[35:0]
DINV[3:0]
Q[35:0]
QINV[3:0]
QVLD[1:0] CK, CK KD[1:0], KD[1:0] CQ[1:0], CQ[1:0] R W MRW PLL RST
Address
Read or write address is registered on CK.
Registered on KD and KD during Write operations.
Registered on KD and KD (along with write data) during Write operations.
Features
- 4Mb x 36 and 8Mb x 18 organizations available.
- Organized as 8 logical memory banks.
- 1333 MHz maximum operating frequency.
- 1.333 BT/s peak transaction rate (in billions per second).
- 192 Gb/s peak data bandwidth (in x36 devices).
- Separate I/O DDR Data Buses.
- Non-multiplexed SDR Address Bus.
- One operation - Read or Write - per clock cycle.
- Certain address/bank restrictions on Read and Write ops.
- Burst of 4 Re.