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GS81314PD18GK - 144Mb SigmaQuad-IVe Burst of 4 Multi-Bank ECCRAM

Download the GS81314PD18GK datasheet PDF. This datasheet also covers the GS81314PD18GK-133 variant, as both devices belong to the same 144mb sigmaquad-ive burst of 4 multi-bank eccram family and are provided as variant models within a single manufacturer datasheet.

General Description

Symbol Description SA[21:1] D[35:0] DINV[3:0] Q[35:0] QINV[3:0] QVLD[1:0] CK, CK KD[1:0], KD[1:0] CQ[1:0], CQ[1:0] R W MRW PLL RST Address

Read or write address is registered on CK.

Registered on KD and KD during Write operations.

D[17:0] - x18 and x36.

Key Features

  • 4Mb x 36 and 8Mb x 18 organizations available.
  • Organized as 8 logical memory banks.
  • 1333 MHz maximum operating frequency.
  • 1.333 BT/s peak transaction rate (in billions per second).
  • 192 Gb/s peak data bandwidth (in x36 devices).
  • Separate I/O DDR Data Buses.
  • Non-multiplexed SDR Address Bus.
  • One operation - Read or Write - per clock cycle.
  • Certain address/bank restrictions on Read and Write ops.
  • Burst of 4 Re.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (GS81314PD18GK-133-GSITechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number GS81314PD18GK
Manufacturer GSI Technology
File Size 266.71 KB
Description 144Mb SigmaQuad-IVe Burst of 4 Multi-Bank ECCRAM
Datasheet download datasheet GS81314PD18GK Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
GS81314PD18/36GK-133/120/106 260-Pin BGA Com & Ind Temp POD I/O 144Mb SigmaQuad-IVe™ Burst of 4 Multi-Bank ECCRAM™ Up to 1333 MHz 1.25V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ Features • 4Mb x 36 and 8Mb x 18 organizations available • Organized as 8 logical memory banks • 1333 MHz maximum operating frequency • 1.333 BT/s peak transaction rate (in billions per second) • 192 Gb/s peak data bandwidth (in x36 devices) • Separate I/O DDR Data Buses • Non-multiplexed SDR Address Bus • One operation - Read or Write - per clock cycle • Certain address/bank restrictions on Read and Write ops • Burst of 4 Read and Write operations • 6 cycle Read Latency • On-chip ECC with virtually zero SER • Loopback signal timing training capability • 1.25V ~ 1.3V nominal core voltage • 1.2V ~ 1.