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GS81314PD37GK - 144Mb SigmaQuad-IVe Burst of 4 Single-Bank ECCRAM

This page provides the datasheet information for the GS81314PD37GK, a member of the GS81314PD19GK-933 144Mb SigmaQuad-IVe Burst of 4 Single-Bank ECCRAM family.

Description

Symbol Description SA[21:1] D[35:0] DINV[3:0] Q[35:0] QINV[3:0] QVLD[1:0] CK, CK KD[1:0], KD[1:0] CQ[1:0], CQ[1:0] R W MRW PLL RST Address

Read or write address is registered on CK.

Registered on KD and KD during Write operations.

D[17:0] - x18 and x36.

Features

  • 4Mb x 36 and 8Mb x 18 organizations available.
  • Organized as a single logical memory bank.
  • 933 MHz maximum operating frequency.
  • 933 MT/s peak transaction rate (in millions per second).
  • 134 Gb/s peak data bandwidth (in x36 devices).
  • Separate I/O DDR Data Buses.
  • Non-multiplexed SDR Address Bus.
  • One operation - Read or Write - per clock cycle.
  • No address/bank restrictions on Read and Write ops.
  • Burst of 4 Read.

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Datasheet preview – GS81314PD37GK

Datasheet Details

Part number GS81314PD37GK
Manufacturer GSI Technology
File Size 263.31 KB
Description 144Mb SigmaQuad-IVe Burst of 4 Single-Bank ECCRAM
Datasheet download datasheet GS81314PD37GK Datasheet
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Full PDF Text Transcription

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GS81314PD19/37GK-933/800 260-Pin BGA Com & Ind Temp POD I/O 144Mb SigmaQuad-IVe™ Burst of 4 Single-Bank ECCRAM™ Up to 933 MHz 1.2V ~ 1.3V VDD 1.2V ~ 1.3V VDDQ Features • 4Mb x 36 and 8Mb x 18 organizations available • Organized as a single logical memory bank • 933 MHz maximum operating frequency • 933 MT/s peak transaction rate (in millions per second) • 134 Gb/s peak data bandwidth (in x36 devices) • Separate I/O DDR Data Buses • Non-multiplexed SDR Address Bus • One operation - Read or Write - per clock cycle • No address/bank restrictions on Read and Write ops • Burst of 4 Read and Write operations • 5 cycle Read Latency • On-chip ECC with virtually zero SER • Loopback signal timing training capability • 1.2V ~ 1.3V nominal core voltage • 1.2V ~ 1.
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