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GS8673ET18BK Datasheet Preview

GS8673ET18BK Datasheet

72Mb SigmaDDR-IIIe Burst of 2 ECCRAM

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GS8673ET18/36BK-675/625/550/500
260-Ball BGA
Commercial Temp
Industrial Temp
72Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
675 MHz–500 MHz
1.35V VDD
1.2V to 1.5V VDDQ
Features
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaDDR-IIIe™ Interface
• Common I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35V nominal VDD
• 1.2V JESD8-16A BIC-3 Compliant Interface
• 1.5V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
SigmaDDR-IIIeFamily Overview
SigmaDDR-IIIe ECCRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS8673ET18/36BK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used to control the data input
registers. Consequently, data input setup and hold windows
can be optimized independently of address and control input
setup and hold windows.
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Speed Bin
-675
-625
-550
-500
Parameter Synopsis
Operating Frequency
675 / 450 MHz
625 / 400 MHz
550 / 375 MHz
500 / 333 MHz
Data Rate (per pin)
1350 / 900 Mbps
1250 / 800 Mbps
1100 / 750 Mbps
1000 / 666 Mbps
Read Latency
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
VDD
1.3V to 1.4V
1.3V to 1.4V
1.25V to 1.4V
1.25V to 1.4V
Rev: 1.06 5/2012
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology




GSI Technology

GS8673ET18BK Datasheet Preview

GS8673ET18BK Datasheet

72Mb SigmaDDR-IIIe Burst of 2 ECCRAM

No Preview Available !

GS8673ET18/36BK-675/625/550/500
4M x 18 (Top View)
1 2 3 4 5 6 7 8 9 10 11 12 13
A
VDD
VDDQ
VDD
VDDQ MCL
MCH
(CFG)
MCL
ZQ
PZT1 VDDQ VDD VDDQ VDD
B
VSS NUIO VSS
NUI
MVQ
MCL
NC
(RSVD)
MCL
(SIOM)
PZT0
NUI
VSS DQ0 VSS
C DQ17 VDDQ NUI VDDQ VSS SA VDD SA VSS VDDQ NUI VDDQ NUIO
D
VSS NUIO VSS
NUI
SA
VDDQ
NC
(288 Mb)
VDDQ
NC
(144 Mb)
NUI
VSS
DQ1
VSS
E DQ16 VDDQ NUI VDD VSS SA VSS SA VSS VDD NUI VDDQ NUIO
F VSS NUIO VSS NUI SA VDD VDDQ VDD SA NUI VSS DQ2 VSS
G DQ15 NUIO NUI NUI VSS SA MZT1 SA VSS NUI NUI DQ3 NUIO
H DQ14 VDDQ NUI VDDQ SA VDDQ R/W VDDQ SA VDDQ NUI VDDQ NUIO
J VSS NUIO VSS NUI VSS SA VSS SA VSS NUI VSS DQ4 VSS
K CQ1 VDDQ VREF VDD KD1 VDD CK VDD KD0 VDD VREF VDDQ CQ0
L CQ1 VSS QVLD1 VSS KD1 VDDQ CK VDDQ KD0 VSS QVLD0 VSS CQ0
M VSS DQ13 VSS NUI VSS SA VSS SA VSS NUI VSS NUIO VSS
N NUIO VDDQ NUI VDDQ DLL VDDQ LD VDDQ MCH VDDQ NUI VDDQ DQ5
P NUIO DQ12 NUI NUI VSS SA MZT0 SA VSS NUI NUI NUIO DQ6
R VSS DQ11 VSS NUI MCH VDD VDDQ VDD RST NUI VSS NUIO VSS
T NUIO VDDQ NUI VDD VSS SA VSS SA VSS VDD NUI VDDQ DQ7
U VSS DQ10 VSS NUI NUI VDDQ AZT1 VDDQ NUI NUI VSS NUIO VSS
V
NUIO VDDQ NUI VDDQ VSS
SA
(x18)
VDD
SA
(B2)
VSS VDDQ NUI VDDQ DQ8
W
VSS DQ9 VSS
NUI
TCK
RLM0
NC
(RSVD)
MCL
TMS
NUI
VSS NUIO VSS
Y
VDD VDDQ VDD VDDQ TDO
ZT RLM1 MCL
TDI VDDQ VDD VDDQ VDD
Notes:
1. Pins 5A, 6B, and 7A are reserved for future use. They must be tied Low.
2. Pins 5R and 9N are reserved for future use. They must be tied High in this device.
3. Pin 6A is defined as mode pin CFG in the pinout standard. It must be tied High in this device to select x18 configuration.
4. Pin 8B is defined as mode pin SIOM in the pinout standard. It must be tied Low in this device to select Common I/O configuration.
5. Pin 6V is defined as address pin SA for x18 devices. It is used in this device.
6. Pin 8V is defined as address pin SA for B2 devices. It is used in this device.
7. Pin 9D is reserved as address pin SA for 144Mb devices. It is a true no-connect in this device.
8. Pin 7D is reserved as address pin SA for 288Mb devices. It is a true no-connect in this device.
9. Pins 5U and 9U are unused in this device. They must be left unconnected or driven Low.
10. Pins 8W and 8Y are reserved for internal use only. They must be tied Low.
11. Pins 7B and 7W are reserved for future use. They are true no-connects in this device.
Rev: 1.06 5/2012
2/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology


Part Number GS8673ET18BK
Description 72Mb SigmaDDR-IIIe Burst of 2 ECCRAM
Maker GSI Technology
Total Page 30 Pages
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